The present invention relates to a dynamic random access memory device having a plurality of one-transistor type memory cells, and more particularly to a memory cell having a three-dimensional structure.
To realize a high integration in a memory device having a plurality of one-transistor memory cells each consisting of one transfer gate transistor and one storage capacitor, various new attempts have been made. For example, in the report entitled "A CORRUGATED CAPACITANCE CELL (CCC) FOR MEGABIT DYNAMIC MOS MEMORIES" by H. Sunami et al., on pages 806 and 807 of the report of IEDM held in December, 1982, part of the storage capacitor is provided by forming a groove-like recess on a single crystal substrate to reduce the cell area. However, in the memory cell, the transfer gate transistor is provided on a major surface of the substrate, and a thick field insulating layer partly embedded in the substrate is necessary for isolating each of memory cells. Therefore, the prior art structure has a restriction to further enhance the integration. Concretely, a area of about 21 microns square (.mu.m.sup.2) in the plan view is necessary to form one memory cell.